In a split-transaction system bus architecture (e.g., see FIG. 1), a system bus cycle can be split into an address phase and a data phase. Preferably, the bus module runs each portion of the cycle semi-independently, releasing the corresponding portion of the bus when that part of the cycle is complete. Once that portion of the bus is released, another bus module can then acquire it and initiate a new cycle in parallel, with the first module completing the rest of its own cycle.
For example, module A in FIG. 1 might acquire the address bus, perform its address cycle, then acquire the data bus, and perform the data cycle. Once module A completes its address sequence, it can release the address bus, whereupon module B can acquire the address bus and begin its own address cycle, while module A is working on its data cycle (e.g., see FIG. 1, with bus modules A, B, coupled to Data bus, Address bus).
For this scheme to work, each bus controller must keep track of which cycle is being executed, and determine when both halves are successfully finished, before the cycle is retired. It also needs to snoop the system bus for other modules which are attempting to access the same resource. If a second module tries to access an address for which the first module has already successfully completed an address phase, but not the data phase, the first module must force the second module to retract this request until the first module retires its own cycle. This process is known as a "retry response". The second module will withdraw its cycle and try it again later, by which time the first module may have retired its own cycle.
To implement this technique, a bus module should store the address of the resource it is accessing in a "Cycle Tag" once it has successfully completed its address phase. After that, it compares subsequent address bus cycles to the contents of the Cycle Tag, and, if a match is detected, issues appropriate retry responses to the requesting bus module. Once its own data phase is complete and the cycle is retired, the tag entry is cleared and subsequent address cycles are ignored (e.g., see FIG. 2, Bus Module logic BM, with Cycle Tag unit 2-CT). Thus, an object hereof is to implement split-transaction bus cycles, especially for "Retry" between bus modules. A related object is to do so using cycle tag means adapted to trigger Retry.
Other objects and. advantages of the present invention will be apparent to those skilled in the art.